Due to the rapid growth of chip densities and increasing clock frequencies in modern high performance integrated circuit (IC) designs, power consumption has become an important issue in IC chip design. A large portion of the total power consumption in synchronous IC chips is due to the operation of flip-flops in a clock network. In conventional synchronous designs, all one-bit flip-flops were considered as independent components. However, in recent years, as the process technology has advanced, and the feature size of the IC has shrunk, it has become possible for minimum size clock drivers to trigger more than one flip-flop. As a result, multi-bit flip-flops have been created, wherein multiple one-bit flip-flops are configured to be triggered from a clock signal provided from a single clock driver. Sharing the clock driver among multiple one-bit flip-flops can reduce the total clock dynamic power consumption, and reduce the total area contributed by the multiple flip-flops and clock driver.
FIG. 1 is a block diagram of a conventional 8-bit multi-bit flip-flop 100 that includes a clock driver 101 that receives a global clock signal CLK, and in response, provides local output clock signals CLKM and CLKMN using series-connected clock inverters 102 and 103. The clock signals CLK, CLKM and CLKMN are used to trigger the storage and transfer of data within master and slave latches in the eight 1-bit flip-flops 110-117. Multi-bit flip-flop 100 also includes a scan enable driver 105, that includes an inverter 106 for providing a local scan enable signal SEN in response to a global scan enable signal SE. The scan enable signals SE and SEN are used to select between the data inputs D0-D7 and the scan data inputs SI0-SI7, which are received by 1-bit flip-flops 110-117.
FIG. 2 is a circuit diagram of conventional 1-bit master-slave flip-flop 110, which represents a bit slice of multi-bit flip-flop 100. Note that flip-flops 111-117 are identical to flip-flop 110. Flip-flop 110 includes input select circuit 210, master latch circuit 230, master-to-slave transfer circuit 240, slave latch circuit 250 and output drivers 260 and 270, which are connected as illustrated. The operation of 1-bit master-slave flip-flop 110 is well known. Input select circuit 210 includes p-channel transistors 201-205 and n-channel transistors 211-215. Input select circuit 210 enables a master flop bit MFBN to be provided based on the input data signal D0, the scan input data signal SI0, the scan enable signals SE and SEN, and the local clock signals CLKM and CLKMN. In general, input select circuit 210 drives the master flop bit MFBN during the half clock cycle that the local clock signal CLKMN is low and the local clock signal is high. If the scan enable signal SE is deactivated low, the data signal D0 is inverted to drive the master flop bit MFBN. Conversely, if the scan enable signal is activated high, the scan input data signal SI0 is inverted to drive the master flop bit MFBN.
Master latch circuit 230 includes p-channel transistors 231-234 and n-channel transistors 235-238. Master latch circuit 230 allows the master flop bit MFBN to be latched in response to the local clock signals CLKM and CLKMN, thereby providing a latched master flop bit MFB. Transfer circuit 240 includes p-channel transistor 241 and n-channel transistor 242, which enable the latched master flop bit MFB to be routed as a slave flop bit SFB in response to the global clock signal CLK and the local clock signal CLKM. Slave latch circuit 250 includes p-channel transistors 251-254 and re-channel transistors 255-258, which allow the slave flop bit SFB to be latched, thereby providing the latched slave flop bit SFBN. Output driver 260 includes p-channel transistor 261 and n-channel transistor 262, which provide the Q0 data output signal in response to the latched slave flop bit SFBN. Output driver 270 includes p-channel transistor 271 and n-channel transistor 272, which provide the scan output data signal SO0 in response to the latched slave flop bit SFBN.
A global reset data signal RD, which is applied to transistors 231, 237, 254 and 258, allows the outputs Q0 and SO0 to be reset to logic ‘0’ values (by setting the latched master flop bit MFB to a logic ‘0’ value and the latched slave flop bit SFBN to a logic ‘1’ value) when the reset data signal RD is activated low. This reset function can be eliminated by removing transistors 231, 237, 254 and 258 from flip-flop 110. Thus, 1-bit flip-flop 110 requires 32 transistors when implementing the reset data function, or 28 transistors when not implementing the reset data function.
FIG. 2 also illustrates the details of inverters 102, 103 and 106, which are implemented by p-channel transistors 221-223 and n-channel transistors 224-226, as illustrated, for a total of 6 transistors.
In general, multi-bit flip-flop 100 requires a large number of transistors (i.e., (8×32)+6=262 transistors), thereby requiring a relatively large layout area. In addition, because the global clock signal CLK is required to directly drive transistors corresponding to transistor 242 within each of the 1-bit flip-flops 110-117 (as well as the transistors 221 and 224 of inverter 102), the global clock network has a relatively high capacitance, thereby resulting in high dynamic power requirements and degraded performance within the multi-bit flip-flop 100.
It would therefore be desirable to have in improved multi-bit flip-flop design that reduces the required number of transistors and the associated layout area. It would further be desirable to have an improved multi-bit flip-flop design that reduces the capacitance of the global clock network, thereby reducing the dynamic power requirements and improving performance. It would further be desirable for the improved multi-bit flip-flop design to exhibit an improved data setup time, thereby further improving performance. It would further be desirable for such an improved multi-bit flip-flop to be fabricated using conventional processing techniques.